TLC0838 CDWR data-comparator Mouser Part No 595-TLC0838CDWR

The  TLC0838 use a sample-data-comparator structure that converts differential analog inputs
by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog
common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal
and is compared to ground (single ended), to an adjacent input (differential), or to a common terminal (pseudo
differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative (–)
polarity. When the signal input applied to the assigned positive terminal is less than the signal on the negative
terminal, the converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A particular input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel
pairs. For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act
differentially with any other channel. In addition to selecting the differential mode, the polarity may also be
selected. Either channel of the channel pair may be designated as the negative or positive input.
The common input on the TLC0838 can be used for a pseudodifferential input. In this mode, the voltage on the
common input is considered to be the negative differential input for all channel inputs. This voltage can be any
reference potential common to all channel inputs. Each channel input can then be selected as the positive
differential input. This feature is useful when all analog circuits are biased to a potential other than ground.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. On each low-to-high transition of the
clock input, the data on DI is clocked into the multiplexer-address shift register. The first logic high on the input
is the start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of
the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is
shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The
SAR status output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift
register is disabled for the duration of the conversion.
An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO
comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling
time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog
signal. The comparator output indicates whether the analog input is greater than or less than the resistive-ladder
output. As the conversion proceeds, conversion data is simultaneously output from DO, with the most significant
bit (MSB) first. After eight clock periods, the conversion is complete and SARS goes low.
The TLC0834 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. When SE is held
high on the TLC0838, the value of the LSB remains on the data line. When SE is forced low, the data is then
clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored in the 9-bit shift
register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time, the output circuits
go to the high-impedance state. If another conversion is desired, CS must make a high-to-low transition followed
by address information.
DI and DO can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state

MSB
Mux Settling Time
MSB-First Data LSB Held LSB-First Data
SE Used to Control LSB-First Data
Hi-Z
Hi-Z
tc
Don’t Care
7 6 2 1 0 1 2 3 4 5 6 7
MSB
LSB-First Data MSB-First Data
MSB
Hi-Z
DO
SE
SARS Hi-Z
SEL SEL
+
Bit
0
DIF EVEN 1 0
DI
Bit
Start
CS
Addressing Mux
tsu
tsu
CLK
1 2 3 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Supply voltage, VCC 4.5 5 5.5 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
Clock frequency, f(clock) 10 600 kHz
Clock duty cycle (see Note 2) 40% 60%
Pulse duration, CS high, tw 220 ns
Setup time, CS low, SE low, or data valid before CLK↑, tsu (see Figures 1 and 2) 350 ns
Hold time, data valid after CLK↑, th (see Figure 1) 90 ns
Operating free air temperature TA
C suffix 0 70
Operating free-air temperature, TA °C
I suffix –40 85 °C
NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the
recommended duty-cycle range, the minimum pulse duration (high or low) is 1 µs.

PARAMETER TEST CONDITIONS†
C SUFFIX I SUFFIX
PARAMETER TEST CONDITIONS† UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
UNIT
VOH High level output voltage
VCC = 4.75 V, IOH = –360 µA 2.8 2.4
VOH High-level output voltage V
VCC = 4.75 V, IOH = –10 µA 4.6 4.5
V
VOL Low-level output voltage VCC = 5.25 V, IOL = 1.6 mA 0.34 0.4 V
IIH High-level input current VIH = 5 V, VIH = 5 V 0.005 1 0.005 1 µA
IIL Low-level input current VIL = 0, VIL = 0 –0.005 –1 –0.005 –1 µA
IOH High-level output (source) current VOH = 0, TA = 25°C –6.5 –24 –6.5 –24 mA
IOL Low-level output (sink) current VOL = VCC, TA = 25°C 8 26 8 26 mA
IOZ High-impedance-state output VO = 5 V, TA = 25°C 0.01 3 0.01 3
IOZ µA g
current (DO or SARS) VO = 0, TA = 25°C –0.01 –3 –0.01 –3 µA
Ci Input capacitance 5 pF
Co Output capacitance 5 pF
† All parameters are measured under open-loop conditions with zero common-mode input voltage (unless otherwise specified).
‡ All typical values are at VCC = 5 V, TA = 25°C.

operating characteristics, VCC = 5 V, f(clock) = 250 kHz, tr = tf = 20 ns, TA = 25°C (unless otherwise
noted)
PARAMETER TEST CONDITIONS§ MIN TYP MAX UNIT
Supply-voltage variation error VCC = 4.75 V to 5.25 V ±1/16 ±1/4 LSB
Total unadjusted error (see Note 5) Vref = 5 V, TA = MIN to MAX ±1 LSB
Common-mode error Differential mode ±1/16 ±1/4 LSB
t d Propagation delay time, output MSB-first data
CL = 100 pF
1500
tpd ns g y,
data after CLK↓ (see Note 6 and Figure 2) LSB-first data
CL = 100 pF 600 ns
tdi Output disable time DO or SARS after CS↑ (see Figure 3)
CL = 10 pF, RL = 10 kΩ 250
tdis Output disable time, DO or SARS after CS↑ (see Figure 3) ns CL = 100 pF, RL = 2 kΩ 500 ns
tc Conversion time (multiplexer-addressing time not included) 8 clock
periods
§ All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response
time.